Cracking
the Code of the Apollo Saturn V LVDC Logic Devices
(February
2013)
I spent many late nights
in squinty-eyed examination of the X-rays we took of the LVDC board, and
plowed through hundreds of pages of publicly available documents about
the IBM System/360 looking for clues that would help unravel the convoluted
maze of puzzle pieces and reveal the nature of the LVDC logic devices.
IBM developed the System/360 and the LVDC in tandem, and I expected that
there would be much crossover of the two systems. In the end I found
that these systems had surprisingly little in common in their gate designs,
and some surprising facts emerged.
IBM introduced the System/360
in 1964 with much fanfare. They proudly flaunted the new DTL solid
state logic devices which they called Solid Logic Technology (SLT) and
published photos and descriptions of their new "Hybrid" devices; ceramic
based micro packages with thick film deposited resistors and semiconductor
chips (both transistors and dual diodes) called "Flat Chips" which were
solder ball reflowed upside down directly onto tiny tinned pads going to
lead traces. The DTL gates contained one common anode dual diode
chip, a dual series diode chip, and a transistor. Rather than having
a full circuit completed in the traces inside of the device, the circuit
was divided into modular components, and depending on which pins were selected
or jumped to which other pins, could configure the DTL device to be a NAND
or a NOR, and to have a choice of possible output configurations.
My first approach was to
try to translate this DTL technology to what could be seen in the LVDC,
but despite weeks of postulating dozens of possibilities there were no
complete fits with what was visible. In science, if it doesn't fit
100% to what you expect then you have to reject your hypothesis, and after
about a month I had to abandon the idea that the LVDC logic devices were
DTL. After I accepted this, I went back to square one with a reexamination
of all the data.
One thing that made the LVDC
logic devices so hard to figure out was that one of my initial assumptions
about the LVDC PCB was wrong - the board's device mounting locations were
not universal as I had thought. In fact, each mounting location was
dedicated and wired for a specific type of device package, though there
seems to be no interconnecting between gates within the board, again suggesting
that the gate array would be created within the backplane wiring.
Also, the pinouts on the two types of logic devices on my board were not
the same, and there was no universal Vcc pin, or ground pin. For
example, an input pin on one device would be a jumper point on another.
Within an hour of revisiting the data with a fresh perspective it all came
into focus, that it could have been built on TTL. I speculated that
this was could be a simple, rudimentary, and bare bones form of Transistor-Transistor
Logic, if it was indeed one gate per logic device. The whole LVDC
system may have operated on many different types of gate packages, but
my board contains only NAND/AND gates and NOT (inverter) gates.
The X-rays revealed that
jumpers inside of the PCB layers were critical to completing the gate circuits,
and these critical connections seem to have been intentionally designed
out of the logic devices themselves. But why? The answer is
most likely that if this was TTL technology then it was highly classified
at the time, and probably exclusive for military or government use only.
The complete absence of any documentation about the LVDC hardware would
seem to corroborate this assumption. In the 1960's IBM made
the computers for every branch of the military, and TTL technology was
clearly the future - for use in ICBM's, guidance, and satellites.
They would have expected some espionage - that some of these logic devices
would fall into enemy hands - the Soviets, or the competition. But
if you were to have possession of these logic device packages and broke
them open you would not see anything special in them - just semiconductors
and resistors in broken circuits. Without the primer of jumper connections
needed to make the device active the secrets of how it operated would be
safe.
Another big difference in
this applied DTL System/360 vs. LVDC technology is the scale. The
individual System/360 SLT device packages were much larger (about 12mm
square) than the LVDC device packages (5mm X 7mm) and the SLT film deposited
resistors were also larger and deposited on the top side of the ceramic
base along with the semiconductor traces. The LVDC device packages
had the film resistors deposited on the bottom side of the ceramic base,
connected in circuit to certain pins with the top side, making the total
package much more compact. One thing about deposited thick film resistors
is their inherent sloppiness for value - up to ±30-40% variation
in tolerance - but what was revealed in the SLT devices was that the film
was deposited between two conductive rails set some distance apart, with
an unusual shape to the resistors which seemed to suggested that the resistor
film had been either mechanically or chemically trimmed after being deposited
to tune its specific resistance. There must have been a process to
do this accurizing on a smaller scale, since the resistive elements in
the LVDC devices are very small.
My disclaimer about this
project is that without using destructive methods it is impossible to know
exactly how these LVDC devices were constructed or how they operate, but
I made working models of the NOT and AND gate packages based on the theory
of TTL through what was visible in the X-rays alone. There is also
good evidence to suggest RTL or DTL as a basis for the LVDC system.
